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XCR3032XL 32 Macrocell CPLD
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DS023 (v2.2) September 15, 2008
Product Specification
Features
* * * * * Low power 3.3V 32 macrocell CPLD 4.5 ns pin-to-pin logic delays System frequencies up to 213 MHz 32 macrocells with 750 usable gates Available in small footprint packages - 48-ball CS BGA (36 user I/O pins) - 44-pin VQFP (36 user I/Os) Optimized for 3.3V systems - Ultra-low power operation - Typical Standby Current of 17 A at 25C - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power (FZP) CMOS technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to the CoolRunner XPLA3 family data sheet (DS012) for architecture description
Description
The CoolRunnerTM XPLA3 XCR3032XL device is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates. Pin-to-pin propagation delays are as fast as 4.5 ns with a maximum system frequency of 213 MHz.
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TotalCMOS Design Technique for Fast Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution, both in process technology and design technique. Xilinx(R) CPLDs employ a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, one must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of the XCR3032XL TotalCMOS CPLD (data taken with two resetable up/down, 16-bit counters at 3.3V, 25 C).
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Typical ICC (mA)
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5
0 0 20 40 60 80 100 120 140 160 180 200
Frequency (MHz)
DS023_01_080101
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25C Table 1: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) Typical ICC (mA) 0 0.017 1 0.13 5 0.54 10 1.06 20 2.09 50 5.2 100 10.26 200 20.3
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DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
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DC Electrical Characteristics Over Recommended Operating Conditions
Symbol VOH(2) Parameter(1) Output High voltage Test Conditions VCC = 3.0V to 3.6V, IOH = -8 mA VCC = 2.7V to 3.0V, IOH = -8 mA IOH = -500 A IOL = 8 mA VIN = GND or VCC to 5.5V VIN = GND or VCC to 5.5V VCC = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz Typical 24.5 Min. 2.4 2.0 90% VCC(3) -10 -10 Max. 0.4 10 10 100 0.25 7.5 8 12 10 Unit V V V V A A A mA mA pF pF pF
VOL IIL(4) IIH(4) ICCSB(8) ICC CIN CCLK CI/O
Output Low voltage Input leakage current I/O High-Z leakage current Standby current Dynamic current(5,6) Input pin capacitance(7) Clock input capacitance(7) I/O pin capacitance(7)
Notes: 1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. Typical leakage current is less than 1 A. 5. See Table 1, Figure 1 for typical values. 6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 7. Typical values, not tested. 8. Typical value at 70C.
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_031802
Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25C
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DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-5 Symbol TPD1 TPD2 TCO TSUF TSU1(4) TSU2 TH(4) TWLH(4) TPLH(4) TAPRPW TR(4) TL(4) fSYSTEM(4) TCONFIG(4) TINIT(4) TPOE
(4) (4) (4)
-7 Max. 4.5 5.0 3.5 Min. 3.0 4.3 4.8 0 3.0 5.0 5.0 Max. 7.0 7.5 5.0 20 20 119 30 30 9.3 9.3 8.3 9.3 Min. 3.0 5.4 6.3 0 4.0 6.0 6.0 -
-10 Max. 9.1 10.0 6.5 20 20 95 30 30 11.2 11.2 10.7 11.2 Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter(1, 2) Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time (fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Asynchronous preset/reset pulse width (High or Low) Input rise time Input fall time Maximum system frequency Configuration time(5) ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
Min.
2.5 3.0 3.5 0 2.5 4.0 4.0 -
20 20 213 30 30 7.2 7.2 6.0 6.5
TPOD TPCO
TPAO(4)
Notes: 1. Specifications measured with one output switching. 2. See CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 3 mA at 3.6V. 6. Output CL = 5 pF.
DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
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Internal Timing Parameters
-5 Symbol Buffer Delays TIN TFIN TGCK TOUT TEN TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TPTCK TLOGI1 TLOGI2 TF TLOGI3 TUDA TSLEW Input buffer delay Fast Input buffer delay Global Clock buffer delay Output buffer delay Output buffer enable/disable delay 0.7 2.2 0.7 1.8 4.5 1.6 3.0 1.0 2.7 5.0 2.2 3.1 1.3 3.6 5.7 ns ns ns ns ns Parameter(1, 2) Min. Max. Min. -7 Max. Min. -10 Max. Unit
Internal Register, Product Term, and Combinatorial Delays Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Product term clock delay Internal logic delay (single p-term) Internal logic delay (PLA OR term) 1.0 0.3 2.0 3.0 1.3 1.0 2.0 3.5 2.5 2.0 2.5 1.0 0.5 2.5 4.5 1.6 1.3 2.3 5.0 2.7 2.7 3.2 1.2 0.7 3.0 5.5 2.0 1.6 2.1 6.0 3.3 3.3 4.2 ns ns ns ns ns ns ns ns ns ns ns
Feedback Delays ZIA delay 0.2 2.9 3.5 ns
Time Adders Foldback NAND delay Universal delay Slew rate limited delay 2.0 1.2 4.0 2.5 2.0 5.0 3.0 2.5 6.0 ns ns ns
Notes: 1. These parameters guaranteed by design and characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model.
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DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
S2
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV.
DS023_03_102401
Figure 3: AC Load Circuit
4.5
+3.0V 90%
4.0
10% 0V
TPD (ns)
TR
3.5
TL
1.5 ns
1.5 ns
3.0
1
2
4
8
16
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS023_06_042800
Outputs
DS023_05_061101
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
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Pin Descriptions
Table 2: XCR3032XL User I/O Pins PC44(1) Total User I/O Pins
1.
Table 3: XCR3032XL I/O Pins Function Block VQ44 36 CS48 36 2 2 2 2 2 VQ44 42 43 44 1(2) 2 3 5 6 7(2) 8 10 11 12 13 14 15 35 34 33 32(2) 31 30 28 27 26(2) CS48 A2 A1 C4 B1(2) C2 C1 D3 D1 D2(2) E1 F1 G1 E4 F2 G2 F3 C5 A6 B6 B7(2) D4 C6 D6 D7 E5(2) GND No Connects Table 4: XCR3032XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN VCC PC44(1) 2 1 44 43 32 7 38 13 10(2) 3, 15, 23, 35 22, 30, 42 VQ44 40 39 38 37 26 1 32 7 4(2) 9, 17, 29, 41 16, 24, 36 CS48 A3 B4 A4 B5 E5 B1 B7 D2 C3(2) B3, C7, E2, G4 A5, E3, E6 A7, B2, F6, G3 2 2 Macrocell 10 11 12 13 14 15 16 PC44(1) 31 29 28 27 26 25 24 VQ44 25 23 22 21 20 19 18 CS48 E7 F7 G7 G6 F5 G5 F4
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This is an obsolete package type. It remains here for legacy support only.
Table 3: XCR3032XL I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 PC44(1) 4 5 6 7(2) 8 9 11 12 13(2) 14 16 17 18 19 20 21 41 40 39 38(2) 37 36 34 33 32(2)
Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. JTAG pins.
Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation.
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DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
Device Part Marking
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Device Type Package Speed Operating Range
XCRxxxxXL TQ144 7C
This line not related to device part number
1
Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line:
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Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 3064XL. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes; C1 = CS48, C2 = CSG48.
Ordering Combination Information
Device Ordering and Part Marking Number XCR3032XL-5VQ44C XCR3032XL-5VQG44C XCR3032XL-5CS48C XCR3032XL-5CSG48C XCR3032XL-7VQ44C XCR3032XL-7VQG44C XCR3032XL-7CS48C XCR3032XL-7CSG48C XCR3032XL-7VQ44I XCR3032XL-7VQG44I XCR3032XL-7CS48I XCR3032XL-7CSG48I XCR3032XL-10VQ44C XCR3032XL-10VQG44C XCR3032XL-10CS48C XCR3032XL-10CSG48C XCR3032XL-10VQ44I Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns Pkg. Symbol VQ44 VQG44 CS48 CSG48 VQ44 VQG44 CS48 CSG48 VQ44 VQG44 CS48 CSG48 VQ44 VQG44 CS48 CSG48 VQ44 No. of Pins 44 44 48 48 44 44 48 48 44 44 48 48 44 44 48 48 44 Package Type Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Very Thin Quad Flat Pack (VQFP) Very Thin Quad Flat Pack (VQFP); Pb- Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Very Thin Quad Flat Pack (VQFP) Operating Range(1) C C C C C C C C I I I I C C C C I
DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
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Ordering Combination Information (Continued)
Device Ordering and Part Marking Number XCR3032XL-10VQG44I XCR3032XL-10CS48I XCR3032XL-10CSG48I Speed (pin-to-pin delay) 10 ns 10 ns 10 ns Pkg. Symbol VQG44 CS48 CSG48 No. of Pins 44 48 48 Package Type Very Thin Quad Flat Pack (VQFP); Pb-Free Chip Scale Package (CSP) Chip Scale Package (CSP); Pb-Free Operating Range(1) I I I
Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C
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DS023 (v2.2) September 15, 2008 Product Specification
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XCR3032XL 32 Macrocell CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 CPLD Data Sheets and Application Notes Device Packages Device Package User Guide
Revision History
The following table shows the revision history for this document. Date 11/18/00 02/05/01 04/11/01 Version 1.0 1.1 1.2 Initial Xilinx release. Removed Timing Model. Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers, Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Updated Typical I/V curve, Figure 2: added voltage levels. Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial packages. Added 200 MHz to Figure 1 and Table 1. changed -5 FSYSTEM to 200 MHz, -5 TF to 0.5 ns. Updated THI spec to correct a typo. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement.Updated note 5 in AC Characteristics table lowering typical current draw during configuration. Added voltage and temperature to Figure 2. Increased -5 TPCO to 6.0 (from 5.5 ns) by adding TPTCK parameter to internal timing model. Increased -5 FMAX. Updated Ordering Information format. Updated Device Part Marking. Updated test conditions for IIL and IIH. Updated Package Device Marking Pin 1 orientation. Add solder temperature specification. Add links to data sheets, application notes and packages. Added ICCSB Typical and TAPRPW specifications. Removed TSOL specification. Added note about Pb-free packages. Added Warranty Disclaimer; Added Pb-Free ordering information. Added notes to tables to indicate PC44 and PCG44 packages are obsolete. Removed part number references to the obsolete PC44C and PCG44C packages in the Ordering Combination Information. See Product Discontinuation Notice xcn07022.pdf. Revision
04/19/01 08/27/01
1.3 1.4
01/08/02
1.5
01/06/03
1.6
07/15/03 08/21/03 02/13/04 04/08/05 03/31/06 09/15/08
1.7 1.8 1.9 2.0 2.1 2.2
DS023 (v2.2) September 15, 2008 Product Specification
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